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DS1258Y/AB 128k x 16 Nonvolatile SRAM
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FEATURES
10-Year Minimum Data Retention in the Absence of External Power Data is Automatically Protected During a Power Loss Separate Upper Byte and Lower Byte ChipSelect Inputs Unlimited Write Cycles Low-Power CMOS Read and Write Access Times as Fast as 70ns Lithium Energy Source is Electrically Disconnected to Retain Freshness Until Power is Applied for the First Time Full 10% Operating Range (DS1258Y) Optional 5% Operating Range (DS1258AB) Optional Industrial Temperature Range of -40C to +85C, Designated IND
PIN ASSIGNMENT
CEU CEL DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 GND DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 OE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC WE A16 A15 A14 A13 A12 A11 A10 A9 GND A8 A7 A6 A5 A4 A3 A2 A1 A0
40-Pin Encapsulated Package 740mil Extended
PIN DESCRIPTION
A0 to A16 DQ0 to DQ15
CEU CEL WE OE
VCC GND
- Address Inputs - Data In/Data Out - Chip Enable Upper Byte - Chip Enable Lower Byte - Write Enable - Output Enable - Power (+5V) - Ground
DESCRIPTION
The DS1258 128k x 16 nonvolatile (NV) SRAMs are 2,097,152-bit fully static, NV SRAMs, organized as 131,072 words by 16 bits. Each NV SRAM has a self-contained lithium energy source and control circuitry that constantly monitors VCC for an out-of-tolerance condition. When such a condition occurs, the lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent data corruption. DIP-package DS1258 devices can be used in place of solutions that build NV 128k x 16 memory by utilizing a variety of discrete components. There is no limit on the number of write cycles that can be executed and no additional support circuitry is required for microprocessor interfacing.
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033104
DS1258Y/AB
READ MODE
The DS1258 devices execute a read cycle whenever WE (Write Enable) is inactive (high) and either/both of CEU or CEL (Chip Enables) are active (low) and OE (Output Enable) is active (low). The unique address specified by the 17 address inputs (A0-A16) defines which of the 131,072 words of data is accessed. The status of CEU and CEL determines whether all or part of the addressed word is accessed. If CEU is active with CEL inactive, then only the upper byte of the addressed word is accessed. If CEU is inactive with CEL active, then only the lower byte of the addressed word is accessed. If both the CEU and CEL inputs are active (low), then the entire 16-bit word is accessed. Valid data will be available to the 16 data output drivers within tACC (Access Time) after the last address input signal is stable, providing that CEU , CEL and OE access times are also satisfied. If CEU , CEL , and OE access times are not satisfied, then data access must be measured from the later occurring signal, and the limiting parameter is either tCO for CEU , CEL , or tOE for OE rather than address access.
WRITE MODE
The DS1258 devices execute a write cycle whenever WE and either/both of CEU or CEL are active (low) after address inputs are stable. The unique address specified by the 17 address inputs (A0-A16) defines which of the 131,072 words of data is accessed. The status of CEU and CEL determines whether all or part of the addressed word is accessed. If CEU is active with CEL inactive, then only the upper byte of the addressed word is accessed. If CEU is inactive with CEL active, then only the lower byte of the addressed word is accessed. If both the CEU and CEL inputs are active (low), then the entire 16-bit word is accessed. The write cycle is terminated by the earlier rising edge of CEU and/or CEL , or WE . All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time (tWR) before another cycle can be initiated. The OE control signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output drivers are enabled ( CEU and/or CEL , and OE active) then WE will disable the outputs in tODW from its falling edge.
READ/WRITE FUNCTION Table 1
OE WE CEL CEU
VCC CURRENT ICCO ICCO
H L L L X X X X
H H H H L L L X
X L L H L L H H
X L H L L H L H
DQ0-DQ7 High-Z Output Output High-Z Input
DQ8-DQ15 High-Z Output High-Z Output Input High-Z Input High-Z
CYCLE PERFORMED Output Disabled Read Cycle
ICCO ICCS
Input High-Z High-Z
Write Cycle Output Disabled
DATA RETENTION MODE
The DS1258AB provides full functional capability for VCC greater than 4.75V, and write protects by 4.5V. The DS1258Y provides full functional capability for VCC greater than 4.5V and write protects by 4.25V. Data is maintained in the absence of VCC without any additional support circuitry. The NV static RAMs constantly monitor VCC. Should the supply voltage decay, the NV SRAMs automatically write protect themselves, all inputs become "don't care," and all outputs become high impedance. As VCC falls below approximately 3.0V, a power switching circuit connects the lithium energy source to RAM to
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DS1258Y/AB
retain data. During power-up, when VCC rises above approximately 3.0V, the power switching circuit connects external VCC to RAM and disconnects the lithium energy source. Normal RAM operation can resume after VCC exceeds 4.75V for the DS1258AB and 4.5V for the DS1258Y.
FRESHNESS SEAL
The DS1258 devices are shipped from Dallas Semiconductor with the lithium energy sources disconnected, guaranteeing full energy capacity. When VCC is first applied at a level greater than VTP, the lithium energy source is enabled for battery backup operation.
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground Operating Temperature Range Storage Temperature Range Soldering Temperature -0.3V to +6.0V 0C to +70C, -40C to +85C for Industrial Parts -40C to +70C, -40C to +85C for Industrial Parts See IPC/JEDEC J-STD-020A Specification
* This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER DS1258AB Power Supply Voltage DS1258Y Power Supply Voltage Logic 1 Logic 0 SYMBOL VCC VCC VIH VIL MIN 4.75 4.5 2.2 0.0 TYP 5.0 5.0 MAX 5.25 5.5 VCC +0.8
(tA: See Note 10)
UNITS V V V V NOTES
DC ELECTRICAL CHARACTERISTICS
PARAMETER Input Leakage Current I/O Leakage Current CEU = CEL VIH VCC Output Current @ 2.4V Output Current @ 0.4V Standby Current CEU , CEL =2.2V Standby Current CEU , CEL =VCC - 0.5V Operating Current Write Protection Voltage (DS1258AB) Write Protection Voltage (DS1258Y)
(VCC = 5V 5% for DS1258AB) (tA: See Note 10) (VCC = 5V 10% for DS1258Y)
SYMBOL IIL IIO IOH IOL ICCS1 ICCS2 ICCO1 VTP VTP 4.50 4.25 4.62 4.37 MIN -2.0 -1.0 -1.0 2.0 0.7 150 1.5 300 170 4.75 4.5 TYP MAX +2.0 +1.0 UNITS mA mA mA mA mA mA mA V V NOTES
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DS1258Y/AB
CAPACITANCE
PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN TYP 20 5 MAX 25 10
(tA = +25C)
UNITS pF pF NOTES
AC ELECTRICAL CHARACTERISTICS
PARAMETER Read Cycle Time Access Time
OE
(VCC = 5V 5% for DS1258AB) (tA: See Note 10) (VCC = 5V 10% for DS1258Y)
DS1258AB-70 DS1258Y-70 DS1258AB-100 DS1258Y-100
SYMBOL tRC tACC tOE tCO tCOE tOD tOH tWC tWP tAW tWR1 tWR2 tODW tOEW tDS tDH1 tDH2
MIN 70
MAX 70 35 70
MIN 100
MAX 100 50 100
UNITS ns ns ns ns ns
NOTES
to Output Valid Output Valid or CEU or CEL to Output Valid
CEU or CEL to OE
5 25 5 70 55 0 5 15 25 5 30 0 10
5 35 5 100 75 0 5 15 35 5 40 0 10
5 5
Output High Z from Deselection Output Hold from Address Change Write Cycle Time Write Pulse Width Address Setup Time Write Recovery Time Output High Z from WE Output Active from WE Data Setup Time Data Hold Time
ns ns ns ns ns ns ns ns ns ns ns ns
3 12 13 5 5 4 12 13
READ CYCLE
SEE NOTE 1
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DS1258Y/AB
WRITE CYCLE 1
SEE NOTE 2, 3, 4, 6, 7, 8 AND 12
WRITE CYCLE 2
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DS1258Y/AB
POWER-DOWN/POWER-UP CONDITION
POWER-DOWN/POWER-UP TIMING
PARAMETER
CEU , CEL
(tA: See Note 10)
MIN 0 300 300 2 125 TYP MAX UNITS ms ms ms ms NOTES 11
at VIH before Power-Down
SYMBOL tPD tF tR tREC
VCC slew from VTP to 0V VCC slew from 0V to VTP
CEU , CEL
at VIH after Power-Up
(tA =+25C)
PARAMETER Expected Data Retention Time SYMBOL tDR MIN 10 TYP MAX UNITS years NOTES 9
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery backup mode.
NOTES:
1) WE is high for a Read Cycle. 2) OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high impedance state. 3) tWP is specified as the logical AND of CEU or CEL and WE . tWP is measured from the latter of CEU , CEL or WE going low to the earlier of CEU , CEL or WE going high. 4) tDS is measured from the earlier of CEU or CEL or WE going high. 5) These parameters are sampled with a 5pF load and are not 100% tested. 6) If the CEU or CEL low transition occurs simultaneously with or later than the WE low transition in the output buffers remain in a high impedance state during this period. 7) If the CEU or CEL high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain in high impedance state during this period.
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DS1258Y/AB
8) If WE is low or the WE low transition occurs prior to or simultaneously with the CEU or CEL low transition, the output buffers remain in a high impedance state during this period. 9) Each DS1258 has a built-in switch that disconnects the lithium source until the user first applies VCC. The expected tDR is defined as accumulative time in the absence of VCC starting from the time power is first applied by the user. This parameter is assured by component selection, process control, and design. It is not measured directly during production testing. 10) All AC and DC electrical characteristics are valid over the full operating temperature range. For commercial products, this range is 0C to +70C. For industrial products, this range is -40C to +85C. 11) In a power-down condition the voltage on any pin may not exceed the voltage on VCC. 12) tWR1, tDH1 are measured from WE going high. 13) tWR2, tDH2 are measured from CEU OR CEL going high. 14) DS1258 DIP modules are recognized by Underwriters Laboratory (U.L.(R)) under file E99151.
DC TEST CONDITIONS
Outputs Open Cycle = 200ns All voltages are referenced to ground
AC TEST CONDITIONS
Output Load: 100 pF + 1TTL Gate Input Pulse Levels: 0.0V to 3.0V Timing Measurement Reference Levels Input: 1.5V Output: 1.5V Input pulse Rise and Fall Times: 5ns
ORDERING INFORMATION
DS1258 TTP - SSS - III Operating Temperature Range blank: 0C to 70C IND: -40C to +85C Access Speed 70: 70ns 100: 100ns Package Type blank: 40-pin (600mil) DIP VCC Tolerance AB: 5% Y: 10%
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DS1258Y/AB
DS1258Y/AB NONVOLATILE SRAM 40-PIN, 740-MIL EXTENDED MODULE
PKG DIM A IN. MM B IN. MM C IN. MM D IN. MM E IN. MM F IN. MM G IN. MM H IN. MM J IN. MM K IN. MM 40-PIN MIN 2.080 52.83 0.715 18.16 0.345 8.76 0.085 2.16 0.015 0.38 0.120 3.05 0.090 2.29 0.590 14.99 0.008 0.20 0.015 0.43 MAX 2.100 53.34 0.740 18.80 0.365 9.27 0.115 2.92 0.030 0.76 0.160 4.06 0.110 2.79 0.630 16.00 0.012 0.30 0.025 0.58
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